1. Field of the Invention
This invention relates to testing of digital networks, and, more particularly, to self-testing of digital networks by a system for supplying test vectors to subsystem modules of a system being tested and processing the output from all subsystem modules of the system to produce a signature which can be evaluated to determine the pass/fail status of the system.
2. Description of the Prior Art
In recent years self-testing techniques have been increasingly sought to meet the growing challenge of testing VLSI chips and systems. These techniques fall in two categories, namely, on-line and off-line self-testing. Off-line self-testing requires a source of test stimulii (test vectors), a means for evaluating test responses, and means to control the test procedure and test status reporting. One popular off-line self-testing technique employs feedback shift registers (henceforth abbreviated as FSRs) to generate test vectors and to evaluate test responses. This technique has been called POLYNOMIAL DIVISION self-testing as the FSRs, whether used for test vector generation or response evaluation, perform the process of division by their characteristic polynomial. As shown in FIG. 1, in this technique a functional network 10 to be tested is sandwiched between an FSR 12 on its inputs used as a test vector source, and a second FSR 14 on its outputs used as a response evaluator. Also connected to the output of the test vector generator 12 is a test-end detector 16 for indicating the conclusion of the testing of a particular functional network. A signature verifier 18 receives the output from the test response evaluator 14. A mode select and timing control unit 20 controls the test operation by providing appropriate mode select and timing signals to the FSRs and the signature verifier. During the mission operation (that is when not testing) the FSRs 12 and 14 either become transparent or form input/output registers for the functional network. Upon receiving the self-test command SLFTST 24 from an outside source (not shown), the mode select and timing control unit 20 issues signals to FSRs 12 and 14 over the signal lines 26 and 28 and inserts the FSRs at the functional network's inputs and outputs. The FSR 12 on inputs is configured to generate test vectors and supply them to the functional network over lines 32. Starting from the initial value, called seed, as the dividend, the FSR 12 performs one step of division by its characteristic polynomial in each clock interval. The remainder obtained in each division step is supplied as a test vector to the function under test 10. The sequence of remainders obtained in this way constitutes a pseudo-random binary seqeunce whose period P depends on the number of stages in the FSR, and the characteristic polynomial. The test vector set necessary for testing the functional network usually has length (number of vectors) L equal to or less than P. Thus, the test-end is marked by the occurrence of the test-end pattern in the pseudo-random binary sequence. The test-end detector 16 detects appearance of the test-end pattern over lines 32 and outputs test-end signal 34 to the control unit 20. At this time the control unit 20 outputs a signal 36 to the signature verifier 18.
While the input FSR 12 to configured to generate test vectors, the output FSR 14 is configured to provide a signature needed for evaluation. For response evaluation FSR 14 employs the division of the output from function under test 10 by characteristic polynomial of the FSR to recursively compress the test response data. At the end of test indicated by test-end detector, the output FSR contains that will be called the response signature of the functional network 10 under test. This signature is provided to the signature verifier 18 where it is compared with the expected fault-free signature stored in the signature verifier. If the response signature agrees with the expected signature, the functional network 10 passes the test; otherwise, it fails. The output 42 from the verifier 18 indicates the pass or fail status of the functional network 10. The probability of error escape, that is, a faulty network producing on erroneous response sequence with the same response signature as the fault-free-expected signature, is governed by the number of stages in the output FSR for each function under test in the prior art system described above.